4位移位寄存器veilog代码
4位移位寄存器verilog代码
1.shiter.v
//4位移位寄存器
module shifter(rst,clk_in1,din,clr,dout,clk_1hz);
input clk_in1,din,clr,rst;
output[3:0] dout;
output clk_1hz;
reg[3:0] dout;
reg clk_1hz;
wire clk,clk_test;
//call the clk_div module
clk_div clk_div1(.rst(rst),.clk_in(clk_in1),.clk_out(clk),.clk_test(clk_test));
always @(posedge clk,posedge clr)
begin
if(clr) // clear signal,active-high lever
begin
dout<=4'b0;
end
else
begin
dout<=dout <<1;//输出信号左移一位
dout[0] <=din;//输入信号补充到输出信号的最低位
end
end
always @()
begin
if(clr)
clk_1hz <=0;
else
clk_1hz <=clk_test;//output the clk directly, test whether the div_freq is right or not.
end
endmodule
2.clk_div.v
// 分频器部分 ，获得便于试验观察的时钟信号
module clk_div(rst,clk_in,clk_out,clk_test);
input rst,clk_in;
output clk_out,clk_test;
reg clk_out,clk_test;
reg[25:0] counter;//50_000_000=1011_1110_1011_1100_0010_0000_00
parameter cnt=50_000_000;/// 50MHz is the sys clk,50_000_000=2FAF080
//parameter cnt=4;
always @(posedge clk_in,negedge rst)
begin
if (!rst)
begin
clk_out <=0;
clk_test <=0;
counter <=0;
end
else
begin
counter <=counter+1;
if(counter==cnt/2-1)
begin
clk_out <=!clk_out;
clk_test <=!clk_test;//test the clk_div is work ?
counter <=0;
end
end
end
endmodule
3. modelsim 仿真模块
`timescale 1 ns/ 1 ps
module shifter_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg clk_in1;
reg clr;
reg din;
reg rst;
// wires
wire clk_1hz;
wire [3:0] dout;
// assign statements (if any)
shifter i1 (
// port map - connection between master ports and signals/registers
.clk_1hz(clk_1hz),
.clk_in1(clk_in1),
.clr(clr),
.din(din),
.dout(dout),
.rst(rst)
);
initial
begin
// code that executes only once
// insert code here --> begin
din=0;clr=0;clk_in1=0;rst=1;
#20 rst=0;
#50 rst=1;
#50 clr=1;
#20 clr=0;
#100 din=1;
// #100 clr=1;
// #100 clr=0;
#100 din=0;
#100 din=1;
// --> end
$display("Running testbench");
end
//initial forever #10 clk_in1=~clk_in1;
always #10
clk_in1=~clk_in1;
always
// optional sensitivity list
// @(event1 or event2 or .... eventn)
begin
// code executes for every event on sensitivity list
// insert code here --> begin
@eachvec;
// --> end
end
initial #10000 $stop;
endmodule